A typical prior art flash EPROM cell with a double poly stacked gate structure is illustrated in FIG. 1. Such cell includes a source & drain region (one of which are typically connected to a common bit line), a control gate (poly 2 layer) an intergate dielectric (ONO layer), a floating gate (poly 1 layer) and a gate dielectric (tunnel oxide layer). A channel region lies between the gate dielectric and substrate, and runs lengthwise between the source/drain regions. In a conventional NOR based array architecture of such cells, hot-electron injection induced by a large channel electric field is used to charge the floating gate (poly 1 layer) in such cell. FN tunneling is used to discharge the floating gate, through the application of a large negative voltage to the control gate and a positive voltage to the source or substrate.
A known problem with using FN tunneling for an erase operation with such cell and array architectures is the possibility of an over-erase condition. This is an inevitable limitation resulting from a number of aspects of such architectures, including manufacturing variations, oxide layer wear, erase voltage fluctuations, etc. This condition arises when a threshold voltage V.sub.t of a cell becomes negative as a result of an erase operation performed in the EPROM. The over-erase condition of such cell leads to a number of well-known operational errors, and affects the scalability and reliability of this particular architecture. Consequently, significant research is expended in the field of flash EPROMs to develop cell structures and array operations that minimize the cell threshold variations therein.
Other problems associated with FN tunneling include the fact that such operations typically require two polarities of voltage, and this further necessitates the inclusion of a negative charge pump, thus increasing device size and complexity. Furthermore, manufacturing & processing complexity are relatively high with FN tunneling based EPROMs, since a triple well is also required to sustain the negative erase voltage. An example of such structure is seen in U.S. Pat. No. 5,491,657 to Haddad et. al., which is incorporated by reference herein. Finally, sophisticated embedded erase algorithms are also needed when using FN tunneling erase operations, and this further drives up the cost of such devices. While Haddad et. a indicate (column 6, 11. 44-50) that erasing of flash arrays using hot hole injection (rather than FN tunneling) is known in the art, Haddad et. al. also confirms that the approaches to date have had only limited success and utility since they yield widely varying threshold variations in the erased cells.